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HIGH SPEED 1K X 8 DUAL-PORT STATIC SRAM
Features
x
IDT7130SA/LA IDT7140SA/LA
x
x
High-speed access - Military: 25/35/55/100ns (max.) - Industrial: 55/100ns (max.) - Commercial: 20/25/35/55/100ns (max.) Low-power operation - IDT7130/IDT7140SA -- Active: 550mW (typ.) -- Standby: 5mW (typ.) - IDT7130/IDT7140LA -- Active: 550mW (typ.) -- Standby: 1mW (typ.) MASTER IDT7130 easily expands data bus width to 16-ormore-bits using SLAVE IDT7140
x x x x x x x x
x
On-chip port arbitration logic (IDT7130 Only) BUSY output flag on IDT7130; BUSY input on IDT7140 INT flag for port-to-port communication Fully asynchronous operation from either port Battery backup operation-2V data retention (LA only) TTL-compatible, single 5V 10% power supply Military product compliant to MIL-PRF-38535 QML Industrial temperature range (-40C to +85C) is available for selected speeds Available in 48-pin DIP and LCC, 52-pin PLCC, and 64-pin STQFP and TQFP
Functional Block Diagram
OEL CEL R/WL OER CER R/WR
I/O0L- I/O7L I/O Control BUSYL
(1,2)
I/O Control
I/O0R-I/O7R
,
BUSYR Address Decoder
10
(1,2)
A9L A0L
MEMORY ARRAY
10
Address Decoder
A9R A0R
CEL OEL R/WL
ARBITRATION and INTERRUPT LOGIC
CER OER R/WR
INTL
(2)
INTR
2689 drw 01
(2)
NOTES: 1. IDT7130 (MASTER): BUSY is open drain output and requires pullup resistor. IDT7140 (SLAVE): BUSY is input. 2. Open drain output: requires pullup resistor.
JUNE 2000
1
DSC-2689/10
(c)2000 Integrated Device Technology, Inc.
IDT7130SA/LA and IDT7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Description
The IDT7130/IDT7140 are high-speed 1K x 8 Dual-Port Static RAMs. The IDT7130 is designed to be used as a stand-alone 8-bit Dual-Port RAM or as a "MASTER" Dual-Port RAM together with the IDT7140 "SLAVE" Dual-Port in 16-bit-or-more word width systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 16-ormore-bit memory system applications results in full-speed, errorfree operation without the need for additional discrete logic. Both devices provide two independent ports with separate control, address, and I/O pins that permit independent asynchronous access for reads or writes to any location in memory. An automatic power down feature, controlled by CE, permits the on chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT's CMOS high-performance tech-nology, these devices typically operate on only 550mW of power. Lowpower (LA) versions offer battery backup data retention capability, with each Dual-Port typically consuming 200W from a 2V battery. The IDT7130/IDT7140 devices are packaged in 48-pin sidebraze or plastic DIPs, LCCs, flatpacks, 52-pin PLCC, and 64-pin TQFP and STQFP. Military grade products are manufactured in compliance with the latest revision of MIL-PRF-38535 QML, making it ideally suited to military temperature applications demanding the highest level of performance and reliability.
Pin Configurations(1,2,3)
CEL R/WL BUSYL INTL OEL A0L A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L I/O3L I/O4L I/O5L I/O6L I/O7L GND 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 IDT7130/40 41 9 P or C 40 (4) 10 P48-1 39 & 11 C48-2(4) 38 12 48-Pin 37 13 DIP (5) 36 14 Top View 35 15 34 16 33 32 17 18 31 19 30 20 29 28 21 22 27 23 26 24 25 VCC CER R/WR BUSYR INTR OER A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R I/O7R INDEX I/O6R I/O5R I/O4R I/O3R A1L I/O2R A2L I/O1R I/O0R A3L
,
2689 drw 02
OEL INTL BUSYL
NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. P48-1 package body is approximately .55 in x .61 in x .19 in. C48-2 package body is approximately .62 in x 2.43 in x .15 in. L48-1 package body is approximately .57 in x .57 in x .68 in. F48-1 package body is approximately .75 in x .75 in x .11 in. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking.
A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L
654 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
48 47 46 45 44 43 42 41 40 39 IDT7130/40L48 or F (4) 38 L48-1 & 37 F48-1(4) 36 48-Pin LCC/ Flatback 35 Top View(5) 34 33 32 31 22 23 24 25 26 27 28 29 30 1
32
R/WL CEL VCC CER
R/WR BUSYR INTR OER
A0L
A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R I/O7R I/O6R
,
2
I/O3L I/O4L I/O5L I/O6L I/O7L GND I/O0R I/O1R I/O2R I/O3R I/O4R I/O5R
2689 drw 03
IDT7130SA/LA and IDT7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
INDEX
76 5432 A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L I/O3L 8 9 10 11 12 13 14 15 16 17 18 19 20
1
52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 OER A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R N/C I/O7R
2689 drw 04
IDT7130/40J J52-1(4) 52-Pin PLCC Top View(5)
21 22 23 24 25 26 27 28 29 30 31 32 33
INDEX OEL A0L A1L A2L A3L A4L A5L A6L N/C A7L A8L A9L N/C I/O0L I/O1L I/O2L
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
N/C N/C N/C INTL BUSYL R/WL CEL VCC VCC CER R/WR BUSYR INTR N/C N/C N/C
I/O4L I/O5L I/O6L I/O7L N/C GND I/O0R I/O1R I/O2R I/O3R I/O4R I/O5R I/O6R
CER R/WR BUSYR INTR N/C
A0L OEL N/C INTL BUSYL R/WL CEL VCC
Pin Configurations(1,2,3) (con't.)
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
IDT7130/40TF or PF PP64-1 & PN64-1(4) 64-Pin STQFP 64-Pin TQFP Top View(5)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
OER A0R A1R A2R A3R A4R A5R A6R N/C A7R A8R A9R N/C N/C I/O7R I/O6R
, 2689 drw 05
NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. J52-1 package body is approximately .75 in x .75 in x .17 in. PP64-1 package body is approximately 10 mm x 10 mm x 1.4mm. PN64-1 package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking.
I/O3L N/C I/O4L I/O5L I/O6L I/O7L N/C GND GND I/O0R I/O1R I/O2R I/O3R N/C I/O4R I/O5R
3
IDT7130SA/LA and IDT7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings(1)
Symbol VTERM(2) Rating Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature DC Output Current Commercial & Industrial -0.5 to +7.0 Military -0.5 to +7.0 Unit V
Recommended DC Operating Conditions
Symbol VCC GND Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 4.5 0 2.2 -0.5(1) Typ. 5.0 0
____ ____
Max. 5.5 0 6.0
(2)
Unit V V V V
2689 tbl 02
TBIAS TSTG IOUT
-55 to +125 -65 to +150 50
-65 to +135 -65 to +150 50
o
C C
VIH VIL
o
0.8
mA
2689 tbl 01
NOTES: 1. VIL (min.) > -1.5V for pulse width less than 10ns. 2. VTERM must not exceed Vcc + 10%.
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%.
Recommended Operating Temperature and Supply Voltage(1,2)
Grade Military Commercial Ambient Temperature -55OC to +125OC 0 C to +70 C -40 C to +85 C
O O O O
GND 0V 0V 0V
Vcc 5.0V + 10% 5.0V + 10% 5.0V + 10%
2689 tbl 03
Capacitance
Symbol CIN COUT
(TA = +25C, f = 1.0MHz)
Conditions VIN = 3dV VOUT = 3dV Max. 9 10 Unit pF pF
2689 tbl 05
Industrial
STQFP and TQFP Packages Only
Parameter(1) Input Capacitance Output Capacitance
NOTES: 1. This is the parameter TA. This is the "instant on" case temperature. 2. Industrial temperature: for specific speeds, packages and powers contact your sales office.
NOTES: 1. This parameter is determined by device characterization but is not production tested. 2. 3dV references the interpolated capacitance when the input and output signals switch from 0V to 3V or from 3V to 0V.
DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VCC = 5.0V 10%)
7130SA 7140SA Symbol |ILI| |ILO| VOL VOL VOH Parameter Input Leakage Current
(1) (1)
7130LA 7140LA Min.
___
Test Conditions VCC = 5.5V, VIN = 0V to VCC VCC - 5.5V, CE = VIH, VOUT = 0V to VCC IOL = 4mA IOL = 16mA IOH = -4mA
Min.
___
Max. 10 10 0.4 0.5
___
Max. 5 5 0.4 0.5
___
Unit A A V V V
2689 tbl 04
Output Leakage Current
___
___
Output Low Voltage (I/O0-I/O7) Open Drain Output Low Voltage (BUSY, INT) Output High Voltage
___
___
___
___
2.4
2.4
NOTE: 1. At Vcc < 2.0V leakages are undefined.
4
IDT7130SA/LA and IDT7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1,5,7) (VCC = 5.0V 10%)
7130X20 (2) 7140X20 (2) Com 'l Only Sym b ol ICC Param eter Dynam ic O p e rating Curre nt (B o th P o rts A c tive ) Test Con dition CEL and CER = V IL, O utp uts Disab le d f = fMAX (3) Version CO M 'L M IL & IND CO M 'L M IL & IND ISB 2 S tand b y Curre nt (O ne P o rt - TTL Le ve l Inp uts) CE"A" = V IL and CE"B" = VIH (6) A c tive P o rt O utp utsDisab le d , f= fMAX (3) CO M 'L M IL & IND CO M 'L M IL & IND CO M 'L M IL & IND SA LA SA LA SA LA SA LA SA LA SA LA SA LA SA LA SA LA SA LA Typ . 110 110
____ ____
7130X25 7140X25 Com 'l & M ilitary Typ . 110 110 110 110 30 30 30 30 65 65 65 65 1.0 0.2 1.0 0.2 60 60 60 60 M ax. 220 170 280 220 65 45 80 60 150 115 160 125 15 5 30 10 145 105 155 115
7130X35 7140X35 Com 'l & M ilitary Typ . 110 110 110 110 25 25 25 25 50 50 50 50 1.0 0.2 1.0 0.2 45 45 45 45 M ax. 165 120 230 170 65 45 80 60 125 90 150 115 15 4 30 10 110 85 145 105
2689 tb l 06a
M ax. 250 200
____ ____
Unit mA
ISB 1
S tand b y Curre nt (B o th P o rts - TTL Le ve l Inp uts)
CEL and CER = V IH f = fMAX (3)
30 30
____ ____
65 45
____ ____
mA
65 65
____ ____
165 125
____ ____
mA
ISB 3
Full S tand b y Curre nt (B o th P o rts CM O S Le v e l Inp uts )
CEL and CER > V CC - 0.2V, V IN > V CC - 0.2V o r V IN < 0.2 V, f = 0 (4) CE"A" < 0.2V and CE"B" > VCC - 0.2V (6) V IN > V CC - 0.2V o r V IN < 0.2V A c tive P o rt O utp uts D is ab le d , f = fMAX (3)
1.0 0.2
____ ____
15 5
____ ____
mA
ISB 4
Full S tand b y Curre nt (O ne P o rt CM O S Le v e l Inp uts )
60 60
____ ____
155 115
____ ____
mA
7130X55 7140X55 Com 'l, In d & M ilitary Sym b ol ICC Param eter Dynam ic O p e rating Curre nt (B o th P o rts A c tive ) CEL and CER = V IL, O utp uts Disab le d f = fMAX (3) Test Con dition Version CO M 'L M IL & IND CO M 'L M IL & IND ISB 2 S tand b y Curre nt (O ne P o rt - TTL Le ve l Inp uts) CE"A" = V IL and CE"B" = VIH (6) A c tive P o rt O utp uts D is ab le d , f= fMAX (3) CO M 'L M IL & IND CO M 'L M IL & IND CO M 'L M IL & IND SA LA SA LA SA LA SA LA SA LA SA LA SA LA SA LA SA LA SA LA Typ . 110 110 110 110 20 20 20 20 40 40 40 40 1.0 0.2 1.0 0.2 40 40 40 40 M ax. 155 110 190 140 65 35 65 45 110 75 125 90 15 4 30 10 100 70 110 85
7130X100 7140X100 Com 'l, In d & M ilitary Typ . 110 110 110 110 20 20 20 20 40 40 40 40 1.0 0.2 1.0 0.2 40 40 40 40 M ax. 155 110 190 140 55 35 65 45 110 75 125 90 15 4 30 10 95 70 110 80 mA mA mA mA Unit mA
ISB 1
S tand b y Curre nt (B o th P o rts - TTL Le ve l Inp uts)
CEL and CER = V IH f = fMAX (3)
ISB 3
Full S tand b y Curre nt (B o th P o rts CM O S Le v e l Inp uts )
CEL and CER > V CC - 0.2V, V IN > V CC - 0.2V o r V IN < 0.2 V, f = 0 (4) CE"A" < 0.2V and CE"B" > VCC - 0.2V (6) V IN > V CC - 0.2V o r V IN < 0.2V A c tive P o rt O utp uts D is ab le d , f = fMAX (3)
ISB 4
Full S tand b y Curre nt (O ne P o rt CM O S Le v e l Inp uts )
2689 tb l 0 6b NOTES: 1. 'X' in part numbers indicates power rating (SA or LA). 2. PLCC and TQFP packages only. 3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tCYC, and using "AC TEST CONDITIONS" of input levels of GND to 3V. 4. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby. 5. Vcc = 5V, TA=+25C for Typ and is not production tested. Vcc DC = 100 mA (Typ) 6. Port "A" may be either left or right port. Port "B" is opposite from port "A". 7. Industrial temperature: for other speeds, packages and powers contact your sales office.
5
IDT7130SA/LA and IDT7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Data Retention Characteristics
Symbol VDR ICCDR Parameter VCC for Data Retention Data Retention Current
(LA Version Only)
7130LA/7140LA Test Condition Min. 2.0 MIL. & IND.
___
Typ.(1)
___
Max.
___
Unit V A
100 100
___
4000 1500
___
VCC = 2.0V, CE > VCC -0.2V tCDR tR(3)
(3)
COM'L.
___
Chip Deselect to Data Retention Time Operation Recovery Time
VIN > VCC -0.2V or VIN < 0.2V
0 tRC(2)
ns ns
2689 tbl 07
___
___
NOTES: 1. VCC = 2V, TA = +25C, and is not production tested. 2. tRC = Read Cycle Time 3. This parameter is guaranteed but not production tested.
Data Retention Waveform
DATA RETENTION MODE VDR 2.0V
VCC
4.5V tCDR
4.5V tR
CE VIH
VDR VIH
2692 drw 06 ,
6
IDT7130SA/LA and IDT7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
AC Test Conditions
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 5ns 1.5V 1.5V Figures 1,2 and 3
2689 tbl 08
5V 1250 DATAOUT 775 30pF*
*100pF for 55 and 100ns versions
5V 1250 DATAOUT 775 5pF*
Figure 1. Output Test Load
Figure 2. Output Test Load (for tHZ, tLZ, tWZ, and tOW) * including scope and jig
5V 270 BUSY or INT 30pF*
*100pF for 55 and 100ns versions
2689 drw 07
Figure 3. BUSY and INT AC Output Test Load
7
IDT7130SA/LA and IDT7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Supply Voltage Range(3,5)
7130X20(2) 7140X20(2) Com'l Only Symbol READ CYCLE tRC tAA tACE tAOE tOH tLZ tHZ tPU tPD Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Output Hold from Address Change Output Low-Z Time
(1,4)
7130X25 7140X25 Com'l & Military Min. Max.
7130X35 7140X35 Com'l & Military Min. Max. Unit
Parameter
Min.
Max.
20
____
____
25
____
____
35
____
____
ns ns ns ns ns ns ns ns ns
2689 tbl 09a
20 20 11
____
25 25 12
____
35 35 20
____
____
____
____
____
____
____
3 0
____
3 0
____
3 0
____
____
____
____
Output High-Z Time (1,4) Chip Enable to Power Up Time (4) Chip Disable to Power Down Time
(4)
10
____
10
____
15
____
0
____
0
____
0
____
20
25
35
7130X55 7140X55 Com'l, Ind & Military Symbol READ CYCLE tRC tAA tACE tAOE tOH tLZ tHZ tPU tPD Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Output Hold from Address Change Output Low-Z Time(1,4) Output High-Z Time
(1,4) (4) (4)
7130X100 7140X100 Com'l, Ind & Military Min. Max. Unit
Parameter
Min.
Max.
55
____
____
100
____
____
ns ns ns ns ns ns ns ns ns
2689 tbl 09b
55 55 25
____
100 100 40
____
____
____
____
____
3 5
____
10 5
____
____
____
25
____
40
____
Chip Enable to Power Up Time
0
____
0
____
Chip Disable to Power Down Time
50
50
NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage Output Test Load (Figure 2). 2. PLCC, TQFP and STQFP packages only. 3. 'X' in part numbers indicates power rating (SA or LA). 4. This parameter is guaranteed by device characterization, but is not production tested. 5. Industrial temperature: for other speeds, packages and powers contact your sales office.
8
IDT7130SA/LA and IDT7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle No. 1, Either Side(1)
tRC ADDRESS tAA tOH DATAOUT BUSYOUT tBDDH (2,3)
2689 drw 08
tOH DATA VALID
PREVIOUS DATA VALID
NOTES: 1. R/W = VIH, CE = VIL, and is OE = VIL. Address is valid prior to the coincidental with CE transition LOW. 2. tBDD delay is required only in the case where the opposite port is completing a write operation to the same the address location. For simultaneous read operations, BUSY has no relationship to valid output data. 3. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
Timing Waveform of Read Cycle No. 2, Either Side(3)
tACE
CE
tAOE (4)
tHZ (2)
OE tLZ (1) DATAOUT ICC CURRENT ISS tPU tLZ 50%
(1)
tHZ (2) VALID DATA tPD(4) 50%
2689 drw 09
NOTES: 1. Timing depends on which signal is asserted last, OE or CE. 2. Timing depends on which signal is deaserted first, OE or CE. 3. R/W = VIH and OE = VIL, and the address is valid prior to or coincidental with CE transition LOW. 4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
9
IDT7130SA/LA and IDT7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Supply Voltage Range(5,6)
7130X20(2) 7140X20(2) Com'l Only Symbol WRITE CYCLE tWC tEW tAW tAS tWP tWR tDW tHZ tDH tWZ tOW Write Cycle Time (3) Chip Enable to End-of-Write Address Valid to End-of-Write Address Set-up Time Write Pulse Width(4) Write Recovery Time Data Valid to End-of-Write Output High-Z Time Data Hold Time Write Enable to Output in High-Z
(1) (1)
7130X25 7140X25 Com'l & Military Min. Max.
7130X35 7140X35 Com'l & Military Min. Max. Unit
Parameter
Min.
Max.
20 15 15 0 15 0 10
____
____
25 20 20 0 15 0 12
____
____
35 30 30 0 25 0 15
____
____
ns ns ns ns ns ns ns ns ns ns ns
2689 tbl 10a
____
____
____
____ ____
____ ____
____ ____
____
____
____
____
____
____
____
____
____
10
____
10
____
15
____
0
____
0
____
0
____
10
____
10
____
15
____
Output Active from End-of-Write (1)
0
0
0
7130X55 7140X55 Com'l, Ind & Military Symbol WRITE CYCLE tWC tEW tAW tAS tWP tWR tDW tHZ tDH tWZ tOW Write Cycle Time (3) Chip Enable to End-of-Write Address Valid to End-of-Write Address Set-up Time Write Pulse Width
(4)
7130X100 7140X100 Com'l, Ind & Military Min. Max. Unit
Parameter
Min.
Max.
55 40 40 0 30 0 20
____
____
100 90 90 0 55 0 40
____
____
ns ns ns ns ns ns ns ns ns ns ns
2689 tbl 10b
____
____
____ ____
____ ____
____
____
Write Recovery Time Data Valid to End-of-Write Output High-Z Time (1) Data Hold Time Write Enable to Output in High-Z Output Active from End-of-Write
(1)
____
____
____
____
25
____
40
____
0
____
0
____
25
____
40
____
(1)
0
0
NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). This parameter is guaranteed by device characterization but is not production tested. 2. PLCC, TQFP and STQFP packages only. 3. For MASTER/SLAVE combination, tWC = tBAA + tWP, since R/W = VIL must occur after tBAA. 4. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus for the required tDW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. 5. 'X' in part numbers indicates power rating (SA or LA). 6. Industrial temperature: for other speeds, packages and powers contact your sales office.
10
IDT7130SA/LA and IDT7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, (R/W Controlled Timing)(1,5,8)
tWC ADDRESS tHZ(7) OE tAW CE tAS(6) R/W tWZ(7) DATA OUT
(4)
tWP(2)
tWR(3)
tHZ(7)
tOW
(4)
tDW DATA IN
tDH
2689 drw 10
Timing Waveform of Write Cycle No. 2, (CE Controlled Timing)(1,5)
tWC ADDRESS tAW CE tAS(6) R/W tDW DATA IN
2689 drw 11
tEW(2)
tWR(3)
tDH
NOTES: 1. R/W or CE must be HIGH during all address transitions. 2. A write occurs during the overlap (tEW or tWP) of CE = VIL and R/W = VIL. 3. tWR is measured from the earlier of CE or R/W going HIGH to the end of the write cycle. 4. During this period, the l/O pins are in the output state and input signals must not be applied. 5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the HIGH impedance state. 6. Timing depends on which enable signal (CE or R/W) is asserted last. 7. This parameter is determined be device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure 2). 8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus for the required tDW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
11
IDT7130SA/LA and IDT7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(7,9)
7130X20(1) 7140X20(1) Com'l Only Symbol BUSY TIMING (For MASTER IDT 7130) tBAA tBDA tBAC tBDC tWH tWDD tDDD tAPS tBDD BUSY Access Time from Address BUSY Disable Time from Address BUSY Access Time from Chip Enable BUSY Disable Time from Chip Enable Write Hold After BUSY(6) Write Pulse to Data Delay
(2) (2)
____
7130X25 7140X25 Com'l & Military Min. Max.
7130X35 7140X35 Com'l & Military Min. Max. Unit
Parameter
Min.
Max.
20 20 20 20
____
____
20 20 20 20
____
____
20 20 20 20
____
ns ns ns ns ns ns ns ns ns
____
____
____
____
____
____
____
____
____
12
____
15
____
20
____
40 30
____
50 35
____
60 35
____
Write Data Valid to Read Data Delay Arbitration Priority Set-up Time (3) BUSY Disable to Valid Data
(4)
____
____
____
5
____
5
____
5
____
25
35
35
BUSY INPUT TIMING (For SLAVE IDT 7140) tWB tWH tWDD tDDD Write to BUSY Input(5) Write Hold After BUSY(6) Write Pulse to Data Delay
(2)
0 12
____
____
0 15
____
____
0 20
____
____
ns ns ns ns
2689 tbl 11a
____
____
____
40 30
50 35
60 35
Write Data Valid to Read Data Delay (2)
____
____
____
7130X55 7140X55 Com'l, Ind & Military Symbol BUSY TIMING (For MASTER IDT 7130) tBAA tBDA tBAC tBDC tWH tWDD tDDD tAPS tBDD BUSY Access Time from Address] BUSY Disable Time from Address BUSY Access Time from Chip Enable BUSY Disable Time from Chip Enable Write Hold After BUSY(6) Write Pulse to Data Delay(2) Write Data Valid to Read Data Delay Arbitration Priority Set-up Time (3) BUSY Disable to Valid Data
(4) (2)
____
7130X100 7140X100 Com'l, Ind & Military Min. Max. Unit
Parameter
Min.
Max.
30 30 30 30
____
____
50 50 50 50
____
ns ns ns ns ns ns ns ns ns
____
____
____
____
____
____
20
____
20
____
80 55
____
120 100
____
____
____
5
____
5
____
55
65
BUSY INPUT TIMING (For SLAVE IDT 7140) tWB tWH tWDD tDDD Write to BUSY Input(5) Write Hold After BUSY(6) Write Pulse to Data Delay
(2) (2)
0 20
____
____
0 20
____
____
ns ns ns ns
2689 tbl 11b
____
____
80 55
120 100
Write Data Valid to Read Data Delay
____
____
NOTES: 1. PLCC, TQFP and STQFP packages only. 2. Port-to-port delay through RAM cells from the writing port to the reading port, refer to "Timing Waveform of Write with Port -to-Port Read and BUSY." 3. To ensure that the earlier of the two ports wins. 4. tBDD is a calculated parameter and is the greater of 0, tWDD - tWP (actual) or tDDD - tDW (actual). 5. To ensure that a write cycle is inhibited on port 'B' during contention on port 'A'. 6. To ensure that a write cycle is completed on port 'B' after contention on port 'A'. 7. 'X' in part numbers indicates power rating (S or L). 8. Industrial temperature: for other speeds, packages and powers contact your sales office.
12
IDT7130SA/LA and IDT7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Port-to-Port Read and BUSY(2,3,4)
tWC ADDR"A" MATCH tWP R/W"A" tDW DATAIN"A" tAPS ADDR"B" tBAA BUSY"B" tWDD DATAOUT"B" tDDD
2689 drw 12 (1)
tDH
VALID
MATCH tBDA tBDD
VALID
NOTES: 1. To ensure that the earlier of the two ports wins. tBDD is ignored for slave (IDT7140). 2. CEL = CER = VIL 3. OE = VIL for the reading port. 4. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is opposite from port "A".
Timing Waveform of Write with BUSY(3)
tWP R/W"A" tWB BUSY"B" tWH(1) R/W"B"
, (2)
NOTES: 1. tWH must be met for both BUSY Input (IDT7140, slave) or Output (IDT7130 master). 2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH. 3. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is oppsite from port "A".
2689 drw 13
13
IDT7130SA/LA and IDT7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of BUSY Arbitration Controlled by CE Timing(1)
ADDR
'A'
AND 'B' CE'B' tAPS (2) CE'A' tBAC
ADDRESSES MATCH
tBDC
BUSY'A'
2689 drw 14
Timing Waveform by BUSY Arbitration Controlled by Address Match Timing(1)
tRC OR tWC ADDR'A' tAPS ADDR'B' tBAA BUSY'B'
2689 drw 15 (2)
ADDRESSES MATCH
ADDRESSES DO NOT MATCH
tBDA
NOTES: 1. All timing is the same for left and right ports. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 2. If tAPS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (7130 only).
AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(2,3)
7130X20(1) 7140X20(1) Com'l Only Symbol INTERRUPT TIMING tAS tWR tINS tINR Address Set-up Time Write Recovery Time Interrupt Set Time Interrupt Reset Time 0 0
____ ____
7130X25 7140X25 Com'l & Military Min. Max.
7130X35 7140X35 Com'l & Military Min. Max. Unit
Parameter
Min.
Max.
0 0
____
____
0 0
____
____
ns ns ns ns
2689 tbl 12a
____
____
____
20 20
25 25
25 25
____
____
____
NOTES: 1. PLCC, TQFP and STQFP package only. 2. 'X' in part numbers indicates power rating (SA or LA). 3. Industrial temperature: for other speeds, packages and powers contact your sales office.
14
IDT7130SA/LA and IDT7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical characteristics Over the Operating Temperature and Supply Voltage Range(1,2)
7130X55 7140X55 Com'l, Ind & Military Symbol INTERRUPT TIMING tAS tWR tINS tINR Address Set-up Time Write Recovery Time Interrupt Set Time Interrupt Reset Time 0 0
____ ____
7130X100 7140X100 Com'l, Ind & Military Min. Max. Unit
Parameter
Min.
Max.
0 0
____
____
ns ns ns ns
2689 tbl 12b
____
____
45 45
60 60
____
____
NOTES: 1. 'X' in part numbers indicates power rating (SA or LA). 2. Industrial temperature: for other speeds, packages and powers contact your sales office.
Timing Waveform of Interrupt Mode(1) INT Set:
tWC ADDR'A' INTERRUPT ADDRESS tAS(3) R/W'A' tINS (3) INT'B'
2689 drw 16 (2)
tWR (4)
INT Clear:
tRC ADDR'B' tAS OE'B' tINR INT'A'
2689 drw 17 (3)
INTERRUPT CLEAR ADDRESS
(3)
NOTES:. 1. All timing is the same for left and right ports. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 2. See Interrupt Truth Table II. 3. Timing depends on which enable signal (CE or R/W) is asserted last. 4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
15
IDT7130SA/LA and IDT7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Truth Tables Truth Table I Non-Contention Read/Write Control(4)
Inputs(1) R/W X X L H H CE H H L L L OE X X X L H D0-7 Z Z DATAIN DATAOUT Z Function Port Disabled and in Power-Down Mode, ISB2 or ISB4 CER = CEL = VIH, Power-Down Mode, ISB1 or ISB3 Data on Port Written into Memory(2) Data in Memory Output on Port(3) High Impedance Outputs
2689 tbl 13
NOTES: 1. A0L - A10L * A0R - A10R. 2. If BUSY = L, data is not written. 3. If BUSY = L, data may not be valid, see tWDD and tDDD timing. 4. 'H' = VIH, 'L' = VIL, 'X' = DON'T CARE, 'Z' = HIGH IMPEDANCE
Truth Table II Interrupt Flag(1,4)
Left Port R/WL L X X X CEL L X X L OEL X X X L A9L-A0L 3FF X X 3FE INTL X X L
(3)
Right Port R/WR X X L X CER X L L X OER X L X X A9R-A0R X 3FF 3FE X INTR L(2) H(3) X X Function Set Right INTR Flag Reset Right INTR Flag Set Left INTL Flag Reset Left INTL Flag
2689 tbl 14
H
(2)
NOTES: 1. Assumes BUSYL = BUSYR = VIH 2. If BUSYL = VIL, then No Change. 3. If BUSYR = VIL, then No Change. 4. 'H' = HIGH,' L' = LOW,' X' = DON'T CARE
Truth Table III Address BUSY Arbitration
Inputs CEL X H X L CER X X H L A0L-A9L A0R-A9R NO MATCH MATCH MATCH MATCH Outputs BUSYL(1) H H H (2) BUSYR(1) H H H (2) Function Normal Normal Normal Write Inhibit(3)
2689 tbl 15
NOTES: 1. Pins BUSYL and BUSYR are both outputs for IDT7130 (master). Both are inputs for IDT7140 (slave). BUSYX outputs on the IDT7130 are open drain, not push-pull outputs. On slaves the BUSYX input internally inhibits writes. 2. 'L' if the inputs to the opposite port were stable prior to the address and enable inputs of this port. 'H' if the inputs to the opposite port became stable after the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously. 3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when BUSYR outputs are driving LOW regardless of actual logic level on the pin.
16
IDT7130SA/LA and IDT7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Functional Description
The IDT7130/IDT7140 provides two ports with separate control, address and I/O pins that permit independent access for reads or writes to any location in memory. The IDT7130/IDT7140 has an automatic power down feature controlled by CE. The CE controls onchip power down circuitry that permits the respective port to go into a standby mode when not selected (CE = VIH). When a port is enabled, access to the entire memory array is permitted.
RAMs are being expanded in depth, then the BUSY indication for the resulting array does not require the use of an external AND gate.
Width Expansion with Busy Logic Master/Slave Arrays
When expanding an RAM array in width while using busy logic, one master part is used to decide which side of the RAM array will receive a busy indication, and to output that indication. Any number of slaves to be addressed in the same address range as the master, use the busy signal as a write inhibit signal. Thus on the IDT7130/IDT7140 RAMs the BUSY pin is an output if the part is Master (IDT7130), and the BUSY pin is an input if the part is a Slave (IDT7140) as shown in Figure 3.
DECODER
Interrupts
If the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. The left port interrupt flag (INTL) is asserted when the right port writes to memory location 3FE (HEX), where a write is defined as the CER = R/WR = VIL per Truth Table II. The left port clears the interrupt by access address location 3FE access when CEL = OEL = VIL, R/W is a "don't care". Likewise, the right port interrupt flag (INTR) is asserted when the left port writes to memory location 3FF (HEX) and to clear the interrupt flag (INTR), the right port must access the memory location 3FF. The message (8 bits) at 3FE or 3FF is user-defined, since it is an addressable SRAM location. If the interrupt function is not used, address locations 3FE and 3FF are not used as mail boxes, but as part of the random access memory. Refer to Truth Table II for the interrupt operation.
5V 270
MASTER Dual Port RAM BUSYL
CE BUSYR
SLAVE Dual Port RAM BUSYL
CE BUSYR
5V 270
MASTER Dual Port RAM BUSYL BUSYL
CE BUSYR
SLAVE Dual Port RAM BUSYL
CE BUSYR BUSYR
2689 drw 18
Busy Logic
Busy Logic provides a hardware indication that both ports of the RAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the RAM is "Busy". The BUSY pin can then be used to stall the access until the operation on the other side is completed. If a write operation has been attempted from the side that receives a BUSY indication, the write signal is gated internally to prevent the write from proceeding. The use of BUSY logic is not required or desirable for all applications. In some cases it may be useful to logically OR the BUSY outputs together and use any BUSY indication as an interrupt source to flag the event of an illegal or illogical operation. In slave mode the BUSY pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the BUSY pins HIGH. If desired, unintended write operations can be prevented to a port by tying the BUSY pin for that port LOW. The BUSY outputs on the IDT7130 RAM (Master) are open drain type outputs and require open drain resistors to operate. If these
Figure 3. Busy and chip enable routing for both width and depth expansion with IDT7130 (Master) and IDT7140 (Slave)RAMs.
If two or more master parts were used when expanding in width, a split decision could result with one master indicating busy on one side of the array and another master indicating busy on one other side of the array. This would inhibit the write operations from one port for part of a word and inhibit the write operations from the other port for the other part of the word. The BUSY arbitration, on a Master, is based on the chip enable and address signals only. It ignores whether an access is a read or write. In a master/slave array, both address and chip enable must be valid long enough for a BUSY flag to be output from the master before the actual write pulse can be initiated with either the R/W signal or the byte enables. Failure to observe this timing can result in a glitched internal write inhibit signal and corrupted data in the slave.
17
IDT7130SA/LA and IDT7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Ordering Information
IDT XXXX A Device Type Power 999 Speed A Package A Process/ Temperature Range BLANK I(1) B P C J L48 F PF TF 20 25 35 55 100 Commercial (0C to +70C) Industrial (-40C to +85C) Military (-55C to +125C) Compliant to MIL-PRF-38535 QML 48-pin Plastic DIP (P48-1) 48-pin Sidebraze DIP (C48-2) 52-pin PLCC (J52-1) 48-pin LCC (L48-1) 48-pin Ceramic Flatpack (F48-1) 64-pin TQFP (PN64-1) 64-pin STQFP (PP64-1) Commercial PLCC, TQFP and STQFP Only Commercial & Military Commercial & Military Commercial, Industrial & Military Commercial, Industrial & Military
Speed in nanoseconds
LA SA 7130 7140
Low Power Standard Power 8K (1K x 8-Bit) MASTER Dual-Port RAM 8K (1K x 8-Bit) SLAVE Dual-Port RAM
2689 drw 19
NOTE: 1. Industrial temperature range is available on selected PLCC packages in standard temperature. For other speeds, packages and powers contact your sales office.
Datasheet Document History
3/15/99: Initiated datasheet document history Converted to new format Cosmetic and typographical corrections Pages 2 and 3 Added additional notes to pin configurations Changed drawing format Page 2 Corrected package number in note 3 Page 2 Fixed pin 1 in DIP pin configuration Replaced IDT logo Page 4 Increased storage temperature parameters Clarified TA parameter Page 5 DC Electrical parameters-changed wording from "open" to "disabled" Changed 500mV to 0mV in notes CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-5166 fax: 408-492-8674 www.idt.com for Tech Support: 831-754-4613 DualPortHelp@idt.com
6/8/99: 8/2/99: 9/29/99: 11/10/99: 6/23/00:
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
18

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